1. Field of the Invention
The embodiments of the invention relate to a semiconductor device, and more particularly, to a clock gating cell. Although embodiments of the invention are suitable for a wide scope of applications, it is particularly suitable for gating a clock signal in circuits having double edge triggered flip-flops.
2. Discussion of the Related Art
In general, synchronous digital systems use a clock signal to coordinate data movement within the system. Early digital systems coordinated the movement of data on either a rising or falling edge of the clock signal and were known as single edge triggered (SET). A single edge triggered flip-flop loads data provided at an input thereof on one of the rising and falling edge of the clock signal.
The components of a related art digital system include transistors that change state at each clock signal. When a component changes state, it consumes power. However not all state changes of the component are necessary to the proper function of the digital system. A component of a digital system may respond to a clock signal and change states thus losing power at a time period when its output is not being used by the system. Unnecessary state changes cause inefficiency because of energy loss is in the form of heat.
The related art digital system may use a clock gating technique to reduce power consumption and prevent individual logic devices from switching states when not in use. When a clock signal is gated prior to being inputted to a logic device, the gated clock signal does not cause the logic device to change state. Clock gating effectively disables the logic device during a time period when the logic device is not needed for the current operation of the digital circuit.
FIG. 1 is a schematic diagram of an integrated clock gating cell (ICG) according to the related art. Referring to FIG. 1, the ICG consists of an AND gate 100. The ICG 100 responds to an enable signal 120 and a clock signal 110 to provide a gated clock signal 130. The clock signal 130 is a switching signal that can be used to synchronize devices in the synchronous digital circuit. The enable signal 120 is controlled by external logic and toggles from low to high to enable the gated clock signal 130. When both the enable signal 120 and the clock signal 110 are high, the gated clock signal 130 is high. When the enable signal 120 is low, the gated clock signal 130 remains low.
Thus, in the related art ICG 100 of FIG. 1, the gated clock signal 130 tracks the clock signal 110 when the enable signal 120 is high. In contrast, when the enable signal 120 is low, the gated clock signal 130 remains low in spite of the transitions in the clock signal 110. However, the related art ICG 100 of FIG. 1 causes a glitch on the enable signal 120 while the clock signal 110 is high to propagate to the connected components through to the gated clock signal 130, thereby causing incorrect data to be loaded in the components clocked by the gated clock signal 130.
FIG. 2 is a schematic diagram of another related art ICG for use in a SET system. Referring to FIG. 2, the related art ICG 200 includes an AND gate 210 and a latch 220 of opposite polarity (i.e. negative latch for rising edge triggered systems and positive latch for falling edge triggered systems) to eliminate glitches. A clock signal 230 is provided to a first input of the latch 220 and to a first input of the AND gate 210. An enable signal 240 is provided at a second input of the latch 220 and the output from the latch 220 is provided to a second input of the AND gate 210. The output from the AND gate 210 is a gated clock signal 250.
According to the related art ICG 200 of FIG. 2, for rising edge triggered systems, the latch 220 is used to remove any glitching from the gated clock output 250. While the clock signal 230 is high or at logic 1, the latch 220 is not transparent, and any glitch on the enable input 240 does not propagate to the output 250 of the ICG 200. While the clock signal 230 is low or at logic 0, the latch 220 is transparent and any glitch propagating through the latch is stopped at the AND gate 210.
According to the related art ICG 200 of FIG. 2, for rising edge triggered systems, the gated clock signal is gated at logic zero i.e. the gated clock signal 250 remains at logic zero if the enable signal 240 remains at “0” for a long enough time. Similarly, the gated clock signal 250 is gated at logic one for falling edge triggered systems.
However, the related art ICG 200 of FIG. 2 uses a SET flip-flop so that data can be loaded only on one of the rising edge and the falling edge of the clock signal 230. To achieve higher data loading rate, it is desirable to load data on both edges of the clock signal.
To reduce power consumption, recent digital systems use double edge triggered (DET) flip-flops to coordinate data movement between components of the system. A DET flip-flop loads data both at the rising and at the falling edge of the clock signal. These benefits are realized because data can be loaded on both edges of the clock signal rather than only one, hence the same functionality and throughput can be obtained at half the clock frequency.
In a double edge triggered circuit, the rising edges of the clock and the falling edges of the clock signal are functionally equivalent (both cause data to be loaded in the flip-flops). From a purely functional perspective, rising clock edges and falling clock edges are mutually interchangeable. Clock gating can be rethought in terms of clock edges in general, without reference to the rising or falling direction of particular edges: when the clock is gated, there are no clock edges. When the clock is enabled, there are edges in the output clock regardless of their direction. Despite the benefits of DET systems, they are infrequently employed because of their incompatibility with the related art clock gating cells, one of the most common and widely used low power techniques.
FIG. 3 is a timing diagram illustrating the switching of a gated clock signal by the related art ICG cell of FIG. 2 when used in a system with DET flip-flops. Referring to FIG. 3, the clock signal 230 provided at the first input of the ICG 200 switches periodically between logic zero and logic one. For example, the clock signal 230 switches from low to high with a rising edge 231 following a time t=0 and switches back to low with a falling edge 232 prior to a time t=1. The switching of the clock signal 230 repeats periodically over time as shown in FIG. 3.
The enable signal 240 at logic 1 prior to the time t=0 and remaining at logic 1 in the time interval from t=0 to t=1 enables the related art ICG 200 to output the gated clock signal 250. Thus, the gated clock signal 250 follows the clock signal 230 in the time interval from t=0 to t=1 with a rising edge 251 following the rising edge 231 of the clock signal 230 and a falling edge 252 following the falling edge 232 of the clock signal.
At a time t=1, the enable signal 240 is switched to low with a falling edge 242 and remains low until a time t=2. Thus, during the time between t=1 and t=2, the related art ICG 200 gates the clock signal at a low value in accordance with the state of the gated clock signal 250 at time t=1.
At time t=2 shortly after a rising edge 235 of the clock signal 230, the enable signal 240 is switched back to high with a rising edge 243. The gated clock 250 is enabled by the high level of the enable signal 240 and starts following the clock signal. However, the rising edge 253 of the gated clock signal 250 occurs after a time delay after the rising edge 243 of the enable signal 240, thus much later than the corresponding rising edge 235 of the clock signal. Thereafter, the gated clock signal 250 switches in accordance with the clock signal 230. For example, the next falling edge 254 of the gated clock signal 254 occurs shortly after the falling edge 236 of the clock signal 230.
However, because the first transition of the gated clock signal 250 with the rising edge 253 occurs much later than the corresponding rising edge 235 of the clock signal, the first pulse from the rising edge 253 to the falling edge 254 of the gated clock signal 250 is much narrower than the pulse width of the clock signal 230. This irregular pulse may cause erroneous behavior in the synchronous digital system. For example, components such as DET flip-flops might incorrectly be switched by the gated clock 250 to load data in the middle of the clock cycle.
A similar incorrect switching of the DET flip-flops can be observed when the ICG 200 stops the gated clock at logic high.
It is desirable for the gated clock signal 250 to start following the input clock after some delay following the rising edge 243 of the enable signal 240 while preserving the pulse width of the clock signal. However, when the related art ICG 200 is used in conjunction with DET flip-flops, the gated clock signal 240 incorrectly switches from low to high with a long delay after the rising edge 235 of the clock signal 230 but switches back to low shortly after the next falling edge 236 of the clock signal 230. Thus, the related art ICG is not suitable for reliably gating the clock signal for DET flip-flops.